The inventions relate to a semiconductor memory cell, array, architecture and device, and techniques for controlling and/or operating such cell, array and device; and more particularly, in one aspect, to a dynamic random access memory (“DRAM”) cell, array, architecture and device, wherein the memory cell includes an electrically floating body wherein an electrical charge is stored therein.
There is a continuing trend to employ and/or fabricate advanced integrated circuits using techniques, materials and devices that improve performance, reduce leakage current and enhance overall scaling. Semiconductor-on-Insulator (SOI) is a material in which such devices may be fabricated or disposed on or in (hereinafter collectively “on”). Such devices are known as SOI devices and include, for example, partially depleted (PD), fully depleted (FD) devices, multiple gate devices (for example, double or triple gate), and Fin-FET.
One type of dynamic random access memory cell is based on, among other things, the electrically floating body effect of SOI transistors. (See, for example, U.S. Pat. No. 6,969,662, incorporated herein by reference). In this regard, the dynamic random access memory cell may consist of a PD or a FD SOI transistor (or transistor formed in bulk material/substrate) having a channel, which is disposed adjacent to the body. The body region of the transistor is electrically floating in view of the insulation layer (or non-conductive region, for example, in a bulk-type material/substrate) disposed beneath the body region. The state of memory cell is determined by the concentration of charge within the body region of the SOI transistor.
With reference to FIGS. 1A, 1B and 1C, in one embodiment, semiconductor DRAM array 10 includes a plurality of memory cells 12 each consisting of transistor 14 having gate 16, body region 18, which is electrically floating, source region 20 and drain region 22. The body region 18 is disposed between source region 20 and drain region 22. Moreover, body region 18 is disposed on or above region 24, which may be an insulation region (for example, in an SOI material/substrate) or non-conductive region (for example, in a bulk-type material/substrate). The insulation or non-conductive region 24 may be disposed on substrate 26.
Data is written into or read from a selected memory cell by applying suitable control signals to a selected word line(s) 28, a selected source line(s) 30 and/or a selected bit line(s) 32. In response, charge carriers are accumulated in or emitted and/or ejected from electrically floating body region 18 wherein the data states are defined by the amount of carriers within electrically floating body region 18. Notably, the entire contents of the '662 patent, including, for example, the features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are incorporated by reference herein.
As mentioned above, memory cell 12 of DRAM array 10 operates by accumulating in or emitting/ejecting majority carriers (electrons or holes) 34 from body region 18 of, for example, N-channel transistors. (See, FIGS. 2A and 2B). In this regard, accumulating majority carriers (in this example, “holes”) 34 in body region 18 of memory cells 12 via, for example, impact ionization near source region 20 and/or drain region 22, is representative of a logic high or “1” data state. (See, FIG. 2A). Emitting or ejecting majority carriers 34 from body region 18 via, for example, forward biasing the source/body junction and/or the drain/body junction, is representative of a logic low or “0” data state. (See, FIG. 2B).
Notably, for at least the purposes of this discussion, a logic high or State “1” corresponds to an increased concentration of majority carriers in the body region relative to an unprogrammed device and/or a device that is programmed with a logic low or State “0”. In contrast, a logic low or State “0” corresponds to a reduced concentration of majority carriers in the body region relative to an unprogrammed device and/or a device that is programmed with logic high or State “1”.
Conventional reading is performed by applying a small drain bias and a gate bias above the transistor threshold voltage. The sensed drain current is determined by the charge stored in the floating body giving a possibility to distinguish between the states “1” and “0”. A floating body memory device has two different current states corresponding to the two different logical states: “1” and “0”.
In one conventional technique, the memory cell is read by applying a small bias to the drain of the transistor as well as a gate bias which is above the threshold voltage of the transistor. In this regard, in the context of memory cells employing N-type transistors, a positive voltage is applied to one or more word lines 28 to enable the reading of the memory cells associated with such word lines. The amount of drain current is determined/affected by the charge stored in the electrically floating body region of the transistor. As such, some conventional reading techniques sense the amount of the channel current provided/generated in response to the application of a predetermined voltage on the gate of the transistor of the memory cell to determine the state of the memory cell; a floating body memory cell may have two or more different current states corresponding to two or more different logical states (for example, two different current conditions/states corresponding to the two different logical states: “1” and “0”). Other reading techniques are in use.
In the case of a DRAM cell, either with or without a floating body, the memory cell or element is dynamic, meaning that the data state must be periodically sensed and restored or refreshed to maintain data integrity. Often this is done by using on-chip or off-chip timers to initiate a refresh operation at regular intervals. A disadvantage of this approach is that the refresh interval required to refresh a memory cell array is typically not a constant. The refresh interval required to maintain data integrity can be affected by many things including temperature variations, power-supply noise and operation of the array. For example, when dynamic memory elements are placed in an array, they are typically accessed by wordlines (row), sourcelines (row or column) and or bitlines (column) lines. The row address activates a wordline which allows the contents of the memory cells to be communicated to bitlines. This process can partially disturb the content of un-addressed cells, typically due to either capacitive coupling to neighboring wordlines, or in cross-point arrays, due to voltage variations on the bitlines and or wordlines. This process can also partially disturb the content of addressed cells or partially addressed cells. As such, the operation of an array can constitute disturb events, or “disturbs”, that reduce the data retention time of un-accessed cells in the active array. With dynamic memories, disturbs typically remove a signal amount that is proportional to the amount of signal remaining.
One conventional solution is to set the refresh timers for an array to a shorter interval to compensate for worst case disturbs. One disadvantage of this solution is that in low power applications this leads to higher standby current than might be necessary when disturbs to an array are not occurring. Another disadvantage of this solution is that in high performance applications, the refresh operation will typically consume a larger percentage of the available operation bandwidth and may reduce the performance capability of the product.
Another possible solution is to have two separate counters (one for time and one for disturb events) and digitally integrate the two. However, this solution would add significant complexity and cost due to additional digital logic. In addition, this solution does not lend itself well to physically tracking disturbs with respect to the memory cell retention, which is necessary for optimum efficiency.
Yet another approach includes two counters, each of which is set with conservative margins. When either timer expires, a refresh operation is initiated. However, this approach could result in failed memory cells in cases where multiple disturbs occur near the end of the timer period. Conversely, this approach could lead to higher power consumption in the event that no disturbs or many disturbs occur.
FIG. 3A is a schematic diagram of a prior art refresh timer 300. The timer 300 is an analog timer that generates a timer expired (TE) signal 304 after the expiration of an interval that is fixed by the time it takes a stored potential C1a to decay to a predetermined level Vt. The refresh timer 300 includes a switch SWp 308 connected to a voltage V1, which is typically a power supply voltage. A capacitor C1 310 is charged by voltage V1 through switch SWp 308. The capacitor C1 310 is connected through a node C1a to a resistor 306, switch SWp 308, and the input of a logic gate threshold voltage (Vt) detect 302. The potential C1a decays through resistor 306 to potential V2, typically ground. When the potential C1a on C1 310 decays to Vt, the logic gate 302 outputs TE signal 304. Logic gate 302 can be an inverter, for example. TE signal 304 initiates a refresh operation on a memory cell or group of memory cells. The interval between refresh operations is determined by the design of the refresh timer 300 and is not variable.
FIG. 3B illustrates the operation of the refresh timer 300. A signal level (in arbitrary units) is shown on the vertical axis, and time (in arbitrary units) is shown on the horizontal axis. A trigger threshold voltage, Vt, is marked as the first delineation of the vertical signal axis. Looking from the left to the right on the diagram, a potential level of C1 310 (the potential at node C1a) is shown decaying from an initial high level until it reaches Vt. The timer expired signal TE 304 is fired when the voltage at C1a reaches Vt. Also, the refresh timer is reset when the voltage at C1a reaches Vt. This involves recharging capacitor C1 through switch SWp. As shown in FIG. 3B, the interval between timer reset events is fixed. This does not allow for flexibility to reduce the refresh interval when events occur that may reduce the period during which the data integrity of a memory cell can be guaranteed. As a consequence, the fixed interval is typically required to be relatively short to allow for worst-case scenarios, thus usually consuming more power than actually required.
It would be advantageous to have a method and apparatus that efficiently integrates both time and disturb events, and shortens the interval between refresh operations only when and where required. As described above, dynamic memories typically require refresh timers that will fire a ‘refresh needed’ signal. It is desired that this signal occur more frequently if disturb events occur, such as repeated wordline accesses to neighboring wordlines. In addition it is desirable for the effect of a disturb on the refresh timer to closely track the effect of the disturb on the structures being monitored.